counter13.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter13 is
  port(clk:in std_logic;
       co:out std_logic);
end counter13;
architecture count of counter13 is
  signal tempcnt:std_logic_vector(3 downto 0);
begin
  p1:process(clk)
     begin 
       if (clk'event and clk='1') then
         if(tempcnt="1100") then
           tempcnt<="0000";
         else 
           tempcnt<=tempcnt+1;
         end if;
       end if;
     end process p1;
  p2:PROCESS(clk)
     BEGIN
       IF (clk'EVENT AND clk='1') THEN
          IF (tempcnt="1100") THEN
             co<='1';
          ELSE 
             co<='0';
          END IF;
       END IF;
     END PROCESS p2;
END count;