exwhenb.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 14 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY exwhenb IS 
     PORT(in0,in1,in2,in3:IN STD_LOGIC;
          y:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END exwhenb;
ARCHITECTURE exb OF exwhenb IS 
BEGIN
       y <= "11" WHEN in3='1' ELSE
            "10" WHEN in2='1' ELSE
            "01" WHEN in1='1' ELSE
            "00";
END exb;