vectointeger.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
entity vectointeger is
  port(din:in std_logic_vector(7 downto 0);
       flag:out boolean;
       dout:out integer);
end vectointeger;
architecture bevcs of vectointeger is
begin
  process(din)
    variable temp:integer:=0;
  begin 
    flag<=false;
    loop1:for i in 7 downto 0 loop
            temp:=temp*2;
            if (din(i)='1') then
              temp:=temp+1;
            elsif (din(i)/='0') then
              flag<=true;
            end if;
          end loop;
          dout<=temp;
  end process;
end bevcs;