fgshif4.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fgshift4 IS
  PORT(din,clk:IN STD_LOGIC;
       dout:OUT STD_LOGIC);
END fgshift4;
ARCHITECTURE fgshift4x OF fgshift4 IS
  COMPONENT dffx 
    PORT(d,cp:IN STD_LOGIC;
         q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL temp:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
  temp(4)<=din;
  g1:FOR i IN  4 DOWNTO 1  GENERATE
     dfn: dffx PORT MAP (temp(i),clk,temp(i-1));
     END GENERATE;
     dout<=temp(0);
END fgshift4x;