dffx.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY dffx IS
  PORT(d,cp:IN STD_LOGIC;
         q:OUT STD_LOGIC);
END dffx;
ARCHITECTURE dfx OF dffx IS
BEGIN
  PROCESS(cp,d)
  BEGIN
   IF (cp'EVENT AND cp='1') THEN
      q<=d;
   END IF;
  END PROCESS;
END dfx;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY pmpshift4 IS 
  PORT(din,clk:IN STD_LOGIC;
       dout:OUT STD_LOGIC);
END pmpshift4;
ARCHITECTURE strshift4 OF pmpshift4 IS
  COMPONENT dffx
    PORT(d,cp:IN STD_LOGIC;
         q:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL temp:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
  temp(4)<=din;
  dff3:dffx PORT MAP (temp(4),clk,temp(3));             --位置映射
  dff2:dffx PORT MAP (d=>temp(3),cp=>clk,q=>temp(2));   --名称映射
  dff1:dffx PORT MAP (temp(2),q=>temp(1) ,cp=>clk);     --混合映射
  dff0:dffx PORT MAP (temp(1),clk,temp(0));
  dout<=temp(0);
END  strshift4;