csif1.vhd

《CPLD_FPGA设计及应用》课件与实例

library ieee;
use ieee.std_logic_1164.all;
entity csif1 is
  port(a:in std_logic;
       y:out std_logic);
end csif1;
architecture csif of csif1 is
begin
  process(a)
  begin
    if (a='1') then
       y<=a;
    end if;
  end process;
end csif;