vectointeger.vhd

《CPLD_FPGA设计及应用》课件与实例

architecture bevvecinteger of vectointeger is
begin
  process(din)
    variable  temp:integer:=0;
    variable  i:integer:=0;
  begin
    flag<=false;
    loop1:while (i < 8)  loop
            temp:=temp*2;
            if (tempdin(7-i)='1')  then
              temp:=temp+1;
              i:=i+1;
            elsif (tempdin(7-i)/='0') then
              flag<=true;
            end if;
          end loop;
    dout<=temp;
  end process;    
end bevvecinteger;