exwhen.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 10 行

ENTITY  exwhen IS 
   PORT(s1,s2:IN BIT;
       y:OUT BIT);
END exwhen;   
ARCHITECTURE exa OF exwhen IS
BEGIN
      y <= '1'  WHEN   s1 = '0'  ELSE
	           '0'  WHEN  s2 = '0';
END exa;