gdblock.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 15 行

library ieee;
use ieee.std_logic_1164.all;
entity gdblock is
  port(clk,d:in std_logic;
       q,nq:out std_logic);
end gdblock;
architecture bdff of gdblock is
begin
  bk:block(clk'event and clk='1')
     begin
            q<=guarded d;
            nq<=guarded (not d);
     end block bk;
end bdff;