evaluatel.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 15 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY evaluate1  IS
  PORT(a,b:IN STD_LOGIC;
       f1:OUT STD_LOGIC);
END evaluate1;
ARCHITECTURE exevalc OF evaluate1 IS
BEGIN
     PROCESS(a,b)
   BEGIN 
       f1<=a AND b;
       f1<=a NOR b;
   END PROCESS;
END exevalc;