cnt6.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt6 IS 
  PORT(clk:IN STD_LOGIC;
       div25:OUT STD_LOGIC);
END cnt6;
ARCHITECTURE  divcnt OF cnt6 IS
  CONSTANT cst:STD_LOGIC_VECTOR(1 DOWNTO 0):="11";
  SIGNAL temp:STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL clktemp,div2,divtemp:STD_LOGIC;
BEGIN
  clktemp<=clk xor div2;
  p1:PROCESS(clktemp)
     BEGIN
       IF (clktemp'EVENT AND clktemp='1') THEN
          IF (temp=0) THEN
              temp<=cst-1;
              divtemp<='1';
          ELSE
              temp<=temp-1;
              divtemp<='0';
          END IF;
       END IF;
     END PROCESS;
  p2:PROCESS(divtemp)
     BEGIN
       IF (divtemp'EVENT AND divtemp='1') THEN
              div2<=not div2;
       END IF;
     END PROCESS;
  div25<=divtemp;
END divcnt;