multi8.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 42 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY multi8 IS
  PORT(clk:IN STD_LOGIC;
       x,y:IN INTEGER RANGE 0 TO 127;
       f:OUT INTEGER RANGE 0 TO 65535);
END multi8;
ARCHITECTURE multi OF multi8 IS
  TYPE statetype IS(st0,st1,st2);
  SIGNAL state:statetype;
  SIGNAL ytemp:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
  p1:PROCESS
       VARIABLE preg,treg: INTEGER RANGE 0 TO 65535;
       VARIABLE count: INTEGER RANGE 0 TO 7;
     BEGIN
       ytemp<=CONV_STD_LOGIC_vector(y,8);
       WAIT UNTIL clk='1';
       CASE  state IS
         WHEN st0=> state<=st1;         --初始化
                   count:=0;
                   preg:=0;
                   treg:=x;
         WHEN st1=>                  --乘法
                  IF count=7 THEN
                     state<=st2;
                  ELSE 
                    IF ytemp(count)='1' THEN          
                       preg:=preg+treg;
                    END IF;
                       treg:=treg*2;
                       count:=count+1;
                       state<=st1;
                  END IF;
          WHEN st2=> f<=preg;          --输出乘法结果
                    state<=st0;
      END CASE;
    END PROCESS;             
END multi;