cnt5.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 57 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt5 IS 
  PORT(clk:IN STD_LOGIC;
       div3:OUT STD_LOGIC);
END cnt5;
ARCHITECTURE  divcnt OF cnt5 IS
  CONSTANT cst:STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
  CONSTANT limit:STD_LOGIC_VECTOR(1 DOWNTO 0):="01";
  SIGNAL tempr,tempf:STD_LOGIC_VECTOR(1 DOWNTO 0);
  SIGNAL r,f:STD_LOGIC;
BEGIN
  p1:PROCESS(clk)
     BEGIN
       IF (clk'EVENT AND clk='1') THEN
          IF (tempr=cst) THEN
              tempr<=(OTHERS=>'0');
          ELSE
              tempr<=tempr+1;
          END IF;
       END IF;
     END PROCESS;
  p2:PROCESS(clk)
     BEGIN
       IF (clk'EVENT AND clk='0') THEN
          IF (tempf=cst) THEN
              tempf<=(OTHERS=>'0');
          ELSE
              tempf<=tempf+1;
          END IF;
       END IF;
     END PROCESS;
  p3:PROCESS(clk)
     BEGIN
        IF (clk'EVENT AND clk='1') THEN
          IF (tempr=0) THEN
              r<='1';
          ELSIF (tempr=limit) THEN
              r<='0';
          END IF;
       END IF;
     END PROCESS; 
  p4:PROCESS(clk)
     BEGIN
        IF (clk'EVENT AND clk='0') THEN
          IF (tempf=0) THEN
              f<='1';
          ELSIF (tempf=limit) THEN
              f<='0';
          END IF;
       END IF;
     END PROCESS; 
  div3<=r or f;
END divcnt;