detector.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 67 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY detector IS 
PORT (clk, x: IN STD_LOGIC;
              mk: OUT STD_LOGIC);
END detector;
ARCHITECTURE xdetector OF detector IS 
  TYPE states IS (s0, s1, s2, s3, s4, s5, s6, s7);
  SIGNAL  state: states;
BEGIN
PROCESS (x, state)
      BEGIN
          IF  rising_edge(clk)  THEN
				CASE  state  IS
                    WHEN s0 =>  mk <= ′0′;
                         IF (x = ′1′)  THEN
                            state <= s1;
                         ELSE
                             state <= s0;
                         END IF;
                    WHEN s1 =>  mk <= ′0′;
                         IF (x = ′1′)  THEN
                            state <= s2;
                         ELSE
                             state <= s0;
                         END IF;
                     WHEN s2 =>  mk <= ′0′;
                         IF (x = ′0′)  THEN
                            state <= s3;
                         ELSE
                             state <= s2;
                         END IF;
                     WHEN s3 =>  mk <= ′0′;
                         IF (x = ′0′)  THEN
                            state <= s4;
                         ELSE
                             state <= s1;
                         END IF;
                     WHEN s4 =>  mk <= ′0′;
                         IF (x = ′1′)  THEN
                            state <= s5;
                         ELSE
                             state <= s0;
                         END IF;
                     WHEN s5 =>  mk <= ′0′;
                         IF (x = ′0′)  THEN
                            state <= s6;
                         ELSE
                             state <= s2;
                         END IF;
                     WHEN s6 =>  mk <= ′0′;
                         IF (x = ′0′)  THEN
                            state <= s7;
                         ELSE
                             state <= s1;
                         END IF;
                    WHEN s7 =>  mk <= ′1′;
                         IF (x = ′0′)  THEN
                            state <= s0;
                         ELSE
                             state <= s1;
                         END IF;
					END CASE;
				END IF;
       END PROCESS;
END xdetector;