cnt2.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt2 IS 
  PORT(clk:IN STD_LOGIC;
       div6:OUT STD_LOGIC);
END cnt2;
ARCHITECTURE  divcnt OF cnt2 IS
  SIGNAL temp:STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL div6temp:STD_LOGIC;
BEGIN
  PROCESS(clk)
    CONSTANT cst:STD_LOGIC_VECTOR(2 DOWNTO 0):="010";
  BEGIN
    IF (clk'EVENT AND clk='1') THEN
       IF (temp=cst) THEN
           temp<=(OTHERS=>'0');
           div6temp<=NOT div6temp;
       ELSE
           temp<=temp+1;
       END IF;
    END IF;
  END PROCESS;
  div6<=div6temp;
END divcnt;