cnt3.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt3 IS 
  PORT(clk:IN STD_LOGIC;
       div6:OUT STD_LOGIC);
END cnt3;
ARCHITECTURE  divcnt OF cnt3 IS
  SIGNAL temp:STD_LOGIC_VECTOR(2 DOWNTO 0);
  CONSTANT cst:STD_LOGIC_VECTOR(2 DOWNTO 0):="101";
BEGIN
  p1:PROCESS(clk)
     BEGIN
       IF (clk'EVENT AND clk='1') THEN
          IF (temp=cst) THEN
              temp<=(OTHERS=>'0');
          ELSE
              temp<=temp+1;
          END IF;
       END IF;
     END PROCESS;
  p2:PROCESS(clk)
     BEGIN
        IF (clk'EVENT AND clk='1') THEN
          IF (temp<2) THEN
              div6<='1';
          ELSE
              div6<='0';
          END IF;
       END IF;
     END PROCESS; 
END divcnt;