adder2.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder2 IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
       co:OUT STD_LOGIC);
END adder2;
ARCHITECTURE  add OF adder2 IS
  SUBTYPE romword IS STD_LOGIC_VECTOR(2 DOWNTO 0);
  TYPE  romtable IS ARRAY (0 TO 15) OF  romword;
  CONSTANT addertable:romtable:=(
     (B"000"),(B"001"),(B"010"),(B"011"),
     (B"001"),(B"010"),(B"011"),(B"100"),
     (B"010"),(B"011"),(B"100"),(B"101"),
     (B"011"),(B"100"),(B"101"),(B"110"));
  SIGNAL sumtemp:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
  PROCESS(a,b,ci)
    VARIABLE com:STD_LOGIC_VECTOR(3 DOWNTO 0);
     BEGIN
       com:=a & b;
       IF (ci='1') THEN
           sumtemp<=addertable(CONV_INTEGER(com))+'1';
       ELSE
           sumtemp<=addertable(CONV_INTEGER(com));
       END IF;
   END PROCESS;
  sum<=sumtemp(1 DOWNTO 0);
  co<=sumtemp(2);  
END add;