stgraycounter.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY stgraycounter IS
	PORT(clk,reset: IN STD_LOGIC;
				 q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END stgraycounter;
ARCHITECTURE behav OF stgraycounter IS
CONSTANT state0: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0000";
CONSTANT state1: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0001";
CONSTANT state2: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0011";
CONSTANT state3: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0010";
CONSTANT state4: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0110";
CONSTANT state5: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0111";
CONSTANT state6: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0101";
CONSTANT state7: STD_LOGIC_VECTOR(3 DOWNTO 0) :="0100";
CONSTANT state8: STD_LOGIC_VECTOR(3 DOWNTO 0) :="1100";
CONSTANT state9: STD_LOGIC_VECTOR(3 DOWNTO 0) :="1110";
SIGNAL current_state:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL next_state:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			current_state<=state0;
		ELSIF (clk 'EVENT AND CLK='1') THEN
			current_state<=next_state;
		END IF;
	END PROCESS;
	PROCESS(current_state,clk)
	BEGIN
		IF(clk'EVENT AND clk='1') THEN
		  CASE current_state IS
			WHEN state0=>
				next_state<=state1;
			WHEN state1=>
				next_state<=state2;
			WHEN state2=>
				next_state<=state3;
			WHEN state3=>
				next_state<=state4;
			WHEN state4=>
				next_state<=state5;
			WHEN state5=>
				next_state<=state6;
			WHEN state6=>
				next_state<=state7;
			WHEN state7=>
				next_state<=state8;
			WHEN state8=>
				next_state<=state9;
			WHEN state9=>
				next_state<=state0;
			WHEN OTHERS=>next_state<=state0;
		  END CASE;
		END IF;
	END PROCESS;
	q<=current_state;
END behav;