graycounter.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY graycounter IS
	PORT(clk,reset: IN STD_LOGIC;
				 q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END graycounter;
ARCHITECTURE behav OF graycounter IS
SIGNAL temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	PROCESS(clk,reset)
	BEGIN
		IF reset='1' THEN
			temp<="0000";
		ELSIF (clk 'EVENT AND CLK='1') THEN
		  IF (temp="1001")	THEN
		    temp<="0000";
		  ELSE
		    temp<=temp+1;
		  END IF;
		END IF;
	END PROCESS;
	  q(3)<='0' xor temp(0);
	  q(2)<=temp(3) xor temp(2);
	  q(1)<=temp(2) xor temp(1);
	  q(0)<=temp(1) xor temp(0);
END behav;