adcsct.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADCSCT IS
PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         CLK,EOC:IN STD_LOGIC;
         OE,ALE,START:OUT STD_LOGIC;
         ADDR:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
     DATA:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     ST:OUT INTEGER RANGE 15 DOWNTO 0);
END ENTITY ADCSCT;
ARCHITECTURE ADCX OF ADCSCT IS 
TYPE STATE IS (ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7);
SIGNAL CST,NST:STATE:=ST0;
SIGNAL REGL:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ADDRX:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
SIGNAL LDOUT:STD_LOGIC;
BEGIN
   --ADDR<="011";
 PRO:PROCESS(CST,EOC)
     BEGIN
       CASE CST IS
         WHEN ST0=> ST<=0;ALE<='0';START<='0';OE<='0';LDOUT<='0';
              NST<=ST1;
         WHEN ST1=> ST<=1;ALE<= '1';START<='0';OE<='0';LDOUT<='0';
              NST<=ST2;
         WHEN ST2=> ST<=2;ALE<= '1';START<='1';OE<='0';LDOUT<='0';
              NST<=ST3;
         WHEN ST3=> ST<=3;ALE<= '0';START<='1';OE<='0';LDOUT<='0';
              IF (EOC='0') THEN NST<=ST4;
              ELSE  
               NST<=ST3;
              END IF;
         WHEN ST4=> ST<=4;ALE<= '0';START<='0';OE<='0';LDOUT<='0';
              IF (EOC='1') THEN NST<=ST5;
              ELSE  
               NST<=ST4;
              END IF;
         WHEN ST5=> ST<=5;ALE<= '0';START<='0';OE<='1';LDOUT<='0';
              NST<=ST6;
         WHEN ST6=> ST<=6;ALE<= '0';START<='0';OE<='1';LDOUT<='1';
              NST<=ST7;
         WHEN ST7=> ST<=7;ALE<= '0';START<='0';OE<='0';LDOUT<='1';
              NST<=ST0;
         WHEN OTHERS=> NST<=ST0;         
        END CASE;
        END PROCESS;
      PROCESS(CLK)
      BEGIN
        IF (CLK'EVENT AND CLK='1')  THEN
           CST<=NST;
        END IF;
      END PROCESS;
      PROCESS(LDOUT)
      BEGIN
        IF LDOUT='1' AND LDOUT'EVENT THEN
           REGL<=D;
        END IF;
      END PROCESS;
      PROCESS(CLK)
      BEGIN
         IF CLK'EVENT AND CLK='1' THEN
             IF CST=ST0  THEN
                 ADDRX<=ADDRX+1;
             END IF;
         END IF;
            ADDR<=ADDRX;
       END PROCESS;
         DATA<=REGL;
END ADCX;