cnt1.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt1 IS 
  PORT(clk:IN STD_LOGIC;
       div2,div4,div8:OUT STD_LOGIC);
END cnt1;
ARCHITECTURE  divcnt OF cnt1 IS
  SIGNAL temp:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
  PROCESS(clk)
  BEGIN
    IF (clk'EVENT AND clk='1') THEN
       IF (temp="111") THEN
           temp<=(OTHERS=>'0');
       ELSE
           temp<=temp+1;
       END IF;
    END IF;
  END PROCESS;
  div2<=NOT temp(0);
  div4<=NOT temp(1);
  div8<= temp(2);
END divcnt;