half_adder.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 12 行

LIBRARY IEEE;
     USE IEEE.STD_LOGIC_1164.ALL;
     ENTITY half_adder IS 
          PORT (a, b: IN STD_LOGIC;
                s, c: OUT STD_LOGIC);
     END half_adder;
     ARCHITECTURE hadder OF half_adder IS 
     BEGIN
           s <= a XOR b;
           c <= a AND b;
     END hadder ;