full_adder.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
     USE IEEE.STD_LOGIC_1164.ALL;
     ENTITY full_adder IS 
         PORT (a, b, ci: IN STD_LOGIC;
               sum, co: OUT STD_LOGIC);
     END full_adder;
     ARCHITECTURE fadder OF full_adder IS 
       COMPONENT half_adder
      	PORT (a, b: IN STD_LOGIC;
               s, c: OUT STD_LOGIC);
       END COMPONENT;
       COMPONENT or
      	PORT (a, b: IN STD_LOGIC;
               c: OUT STD_LOGIC);
       END COMPONENT;
       SIGNAL s1, c1, c2: STD_LOGIC;
      BEGIN
          u1: half_adder PORT MAP(a, b, s1,c1);
          u2: half_adder PORT MAP(s1, ci, sum, c2);
              u3: or2 PORT MAP (c2, c1, co)
       END fadder;