adder2.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder2 IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
       g,p:OUT STD_LOGIC);
END adder2;
ARCHITECTURE  add OF adder2 IS
  SIGNAL temp:STD_LOGIC;
BEGIN
  sum(0)<=a(0)XOR b(0)XOR ci;
  sum(1)<=a(1)XOR b(1)XOR temp;
  temp<=((a(0)AND b(0))OR(a(0)AND ci)OR(b(0)AND ci));
  g<=(a(1)AND b(1))OR ((a(1)OR b(1))AND(a(0)AND b(0)));
  p<=(a(0)OR b(1))AND (a(0)OR b(0));  
END add;