adder83b.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder83b IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       co:OUT STD_LOGIC);
END adder83b;
ARCHITECTURE  add OF adder83b IS
  COMPONENT adder2
  PORT(a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
       g,p:OUT STD_LOGIC);
  END COMPONENT;
  COMPONENT adder3
  PORT(a,b:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
       g,p:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL g0,g1,g2,g3:STD_LOGIC;
  SIGNAL p0,p1,p2,p3:STD_LOGIC;
  SIGNAL c3,c6:STD_LOGIC;
BEGIN
  u1:adder3
     PORT MAP(a(2 DOWNTO 0),b(2 DOWNTO 0),ci,sum(2 DOWNTO 0),g0,p0);
  u2:adder3
     PORT MAP(a(5 DOWNTO 3),b(5 DOWNTO 3),c3,sum(5 DOWNTO 3),g1,p1);
  u3:adder2
     PORT MAP(a(7 DOWNTO 6),b(7 DOWNTO 6),c6,sum(7 DOWNTO 6),g2,p2);
  c3<=g0 OR (p0 AND ci);
  c6<=g1 OR (p1 AND g0)OR (p1 AND p0)OR (p1 AND p0 AND ci);
  co<=g2 OR (p2 AND g1)OR (p2 AND p1 AND g0)OR (p2 AND p1 AND p0 AND ci);  
END add;