adder83a.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder83a IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       co:OUT STD_LOGIC);
END adder83a;
ARCHITECTURE  add OF adder83a IS
  COMPONENT adder2
  PORT(a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
       g,p:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL g0,g1,g2,g3:STD_LOGIC;
  SIGNAL p0,p1,p2,p3:STD_LOGIC;
  SIGNAL c2,c4,c6:STD_LOGIC;
BEGIN
  u1:adder2
     PORT MAP(a(1 DOWNTO 0),b(1 DOWNTO 0),ci,sum(1 DOWNTO 0),g0,p0);
  u2:adder2
     PORT MAP(a(3 DOWNTO 2),b(3 DOWNTO 2),c2,sum(3 DOWNTO 2),g1,p1);
  u3:adder2
     PORT MAP(a(5 DOWNTO 4),b(5 DOWNTO 4),c4,sum(5 DOWNTO 4),g2,p2);
  u4:adder2
     PORT MAP(a(7 DOWNTO 6),b(7 DOWNTO 6),c6,sum(7 DOWNTO 6),g3,p3);
  c2<=g0 OR(p0 AND ci);
  c4<=g1 OR (p1 AND g0)OR (p1 AND p0 AND ci);
  c6<=g2 OR (p2 AND g1)OR (p2 AND p1 AND g0)OR (p2 AND p1 AND p0 AND ci);
  co<=g3 OR (p3 AND g2)OR (p3 AND p2 AND g1)OR (p3 AND p2 AND p1 AND g0)
         OR (p3 AND p2 AND p1 AND p0 AND ci);  
END add;