adder3.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY adder3 IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
       g,p:OUT STD_LOGIC);
END adder3;
ARCHITECTURE  add OF adder3 IS
  SIGNAL c1,c2,temp0,temp1,temp2:STD_LOGIC;
BEGIN
  sum(0)<=a(0)XOR b(0)XOR ci;
  sum(1)<=a(1)XOR b(1)XOR c1;
  sum(2)<=a(2)XOR b(2)XOR c2;
  c1<=(a(0)AND b(0))OR ((a(0)OR b(0))AND ci);
  c2<=(a(1)AND b(1)) OR temp1 OR temp2;
  temp0<=(a(1)OR b(1));
  temp1<=temp0 AND (a(0)AND b(0));
  temp2<=(a(1)OR b(1))AND (a(0)OR b(0))AND ci;
  g<=(a(2)AND b(2))OR ((a(2)OR b(2))AND(a(1)AND b(1)))
      OR ((a(2)OR b(2))AND temp1); 
  p<=(a(2)OR b(2))AND (a(1)OR b(1))AND (a(0)OR b(0));  
END add;