sub1.vhd

《CPLD_FPGA设计及应用》课件与实例

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY sub1 IS 
  PORT(a,b:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       d:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       co:OUT STD_LOGIC);
END sub1;
ARCHITECTURE  sub OF sub1 IS
  COMPONENT full_adder
  PORT(a,b:IN STD_LOGIC;
       ci:IN STD_LOGIC;
       sum:OUT STD_LOGIC;
       co:OUT STD_LOGIC);
  END COMPONENT;
  SIGNAL temp:STD_LOGIC_VECTOR(7 downto 0);
  SIGNAL cotemp:STD_LOGIC;
BEGIN
  u1:full_adder PORT MAP(a(0),NOT b(0),'1',d(0),cotemp);
  temp(0)<=cotemp;
  g1:FOR i IN 1 TO 7  GENERATE
     fadd: full_adder PORT MAP (a(i),NOT b(i),temp(i-1),d(i),temp(i));
     END GENERATE;
     co<=temp(7);
END sub;