decoder.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 28 行

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity decoder is 
  port(rbk:in std_logic_vector(6 downto 0);
       glt:in std_logic_vector(2 downto 0);
       rcgout:out std_logic);
end decoder;

architecture decoderbk of decoder is 
  signal dcout:std_logic_vector(2 downto 0);
begin
  process(rbk)
  begin 
    case rbk is 
      when "0111111"=> dcout<="110";
      when "1011111"=> dcout<="110";
      when "1101111"=> dcout<="110";
      when "1110111"=> dcout<="110";
      when "1111011"=> dcout<="110";
      when "1111110"=> dcout<="110";
      when "1111111"=> dcout<="110";
      when others=> dcout<="000";
    end case;
  end process;
    rcgout<='1' when dcout>=glt else '0';
end decoderbk;