framesynch.map.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 27 00:55:16 2006 " "Info: Processing started: Thu Jul 27 00:55:16 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off framesynch -c framesynch --convert_bdf_to_vhdl=framesynch.bdf " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off framesynch -c framesynch --convert_bdf_to_vhdl=framesynch.bdf" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "framesynch.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file framesynch.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 framesynch " "Info: Found entity 1: framesynch" {  } { { "D:/my_design/lizi/lzxdesign10/framesynch/framesynch.bdf" "framesynch" "" { Schematic "D:/my_design/lizi/lzxdesign10/framesynch/framesynch.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 27 00:55:19 2006 " "Info: Processing ended: Thu Jul 27 00:55:19 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}