framesynch.hif

《CPLD_FPGA设计及应用》课件与实例

Version 4.1 Build 181 06/29/2004 SJ Full Version
18
OFF
OFF
OFF
OFF
0
# entity
decoder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
decoder.vhd
1144210783
4
# storage
db|framesynch.(3).cnf
db|framesynch.(3).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
barker
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
barker.vhd
1144211705
4
# storage
db|framesynch.(4).cnf
db|framesynch.(4).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
cnt32
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cnt32.vhd
1144243734
4
# storage
db|framesynch.(2).cnf
db|framesynch.(2).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
framecontrol
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
framecontrol.vhd
1144244763
4
# storage
db|framesynch.(1).cnf
db|framesynch.(1).cnf
# internal_option {
AUTO_RESOURCE_SHARING
OFF
PRESERVE_REGISTER
OFF
DUP_REG_EXTRACTION
ON
DUP_LOGIC_EXTRACTION
ON
VHDL_VERILOG_BREAK_LOOPS
OFF
}
# end
# entity
framesynch
# case_insensitive
# source_file
framesynch.bdf
1144244956
23
# storage
db|framesynch.(0).cnf
db|framesynch.(0).cnf
# end
# complete