📄 framesynch.tan.qmsg

📁 《CPLD_FPGA设计及应用》课件与实例
💻 QMSG
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{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 23 " "Warning: Circuit may not operate. Detected 23 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "framecontrol:inst4\|div3\[1\] framecontrol:inst4\|div3co clk 5.6 ns " "Info: Found hold time violation between source  pin or register framecontrol:inst4\|div3\[1\] and destination pin or register framecontrol:inst4\|div3co for clock clk (Hold time is 5.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.500 ns + Largest " "Info: + Largest clock skew is 6.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.600 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 12.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framesynch.bdf" "" "" { Schematic "D:/lzxdesign10/framesynch/framesynch.bdf" { { 48 -96 72 64 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.500 ns) 3.900 ns barker:inst7\|temp\[6\] 2 REG LC1_A11 3 " "Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 3; REG Node = 'barker:inst7\|temp\[6\]'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.600 ns" { clk barker:inst7|temp[6] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/barker.vhd" "" "" { Text "D:/lzxdesign10/framesynch/barker.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(1.400 ns) 6.200 ns decoder:inst2\|reduce_nor~117 3 COMB LC4_A1 1 " "Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC4_A1; Fanout = 1; COMB Node = 'decoder:inst2\|reduce_nor~117'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.300 ns" { barker:inst7|temp[6] decoder:inst2|reduce_nor~117 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.300 ns) 7.600 ns decoder:inst2\|reduce_nor~118 4 COMB LC6_A1 1 " "Info: 4: + IC(0.100 ns) + CELL(1.300 ns) = 7.600 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'decoder:inst2\|reduce_nor~118'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.400 ns" { decoder:inst2|reduce_nor~117 decoder:inst2|reduce_nor~118 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.900 ns) 8.600 ns decoder:inst2\|reduce_nor~119 5 COMB LC8_A1 3 " "Info: 5: + IC(0.100 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC8_A1; Fanout = 3; COMB Node = 'decoder:inst2\|reduce_nor~119'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.000 ns" { decoder:inst2|reduce_nor~118 decoder:inst2|reduce_nor~119 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 11.000 ns framecontrol:inst4\|s~121 6 COMB LOOP LC1_A3 13 " "Info: 6: + IC(0.000 ns) + CELL(2.400 ns) = 11.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4\|s~121'" { { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|s~121 LC1_A3 " "Info: Loc. = LC1_A3; Node framecontrol:inst4\|s~121" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|s~121 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|temq~379 LC2_A3 " "Info: Loc. = LC2_A3; Node framecontrol:inst4\|temq~379" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temq~379 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|temnq~330 LC7_A3 " "Info: Loc. = LC7_A3; Node framecontrol:inst4\|temnq~330" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temnq~330 } "NODE_NAME" } } }  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|s~121 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temq~379 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temnq~330 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.400 ns" { decoder:inst2|reduce_nor~119 framecontrol:inst4|s~121 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 12.500 ns framecontrol:inst4\|clk3 7 COMB LC6_A3 3 " "Info: 7: + IC(0.100 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4\|clk3'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.500 ns" { framecontrol:inst4|s~121 framecontrol:inst4|clk3 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.000 ns) 12.600 ns framecontrol:inst4\|div3co 8 REG LC3_A3 4 " "Info: 8: + IC(0.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4\|div3co'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "0.100 ns" { framecontrol:inst4|clk3 framecontrol:inst4|div3co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.200 ns 73.02 % " "Info: Total cell delay = 9.200 ns ( 73.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 26.98 % " "Info: Total interconnect delay = 3.400 ns ( 26.98 % )" {  } {  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "12.600 ns" { clk barker:inst7|temp[6] decoder:inst2|reduce_nor~117 decoder:inst2|reduce_nor~118 decoder:inst2|reduce_nor~119 framecontrol:inst4|s~121 framecontrol:inst4|clk3 framecontrol:inst4|div3co } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.100 ns - Shortest register " "Info: - Shortest clock path from clock clk to source register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framesynch.bdf" "" "" { Schematic "D:/lzxdesign10/framesynch/framesynch.bdf" { { 48 -96 72 64 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.500 ns) 3.900 ns cnt32:inst\|co 2 REG LC2_A5 5 " "Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst\|co'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.600 ns" { clk cnt32:inst|co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/cnt32.vhd" "" "" { Text "D:/lzxdesign10/framesynch/cnt32.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.400 ns) 6.000 ns framecontrol:inst4\|clk3 3 COMB LC6_A3 3 " "Info: 3: + IC(0.700 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4\|clk3'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.100 ns" { cnt32:inst|co framecontrol:inst4|clk3 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.000 ns) 6.100 ns framecontrol:inst4\|div3\[1\] 4 REG LC4_A3 2 " "Info: 4: + IC(0.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4\|div3\[1\]'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "0.100 ns" { framecontrol:inst4|clk3 framecontrol:inst4|div3[1] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 52.46 % " "Info: Total cell delay = 3.200 ns ( 52.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 47.54 % " "Info: Total interconnect delay = 2.900 ns ( 47.54 % )" {  } {  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "6.100 ns" { clk cnt32:inst|co framecontrol:inst4|clk3 framecontrol:inst4|div3[1] } "NODE_NAME" } } }  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "12.600 ns" { clk barker:inst7|temp[6] decoder:inst2|reduce_nor~117 decoder:inst2|reduce_nor~118 decoder:inst2|reduce_nor~119 framecontrol:inst4|s~121 framecontrol:inst4|clk3 framecontrol:inst4|div3co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "6.100 ns" { clk cnt32:inst|co framecontrol:inst4|clk3 framecontrol:inst4|div3[1] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.000 ns - Shortest register register " "Info: - Shortest register to register delay is 1.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns framecontrol:inst4\|div3\[1\] 1 REG LC4_A3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4\|div3\[1\]'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|div3[1] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.900 ns) 1.000 ns framecontrol:inst4\|div3co 2 REG LC3_A3 4 " "Info: 2: + IC(0.100 ns) + CELL(0.900 ns) = 1.000 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4\|div3co'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.000 ns" { framecontrol:inst4|div3[1] framecontrol:inst4|div3co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 90.00 % " "Info: Total cell delay = 0.900 ns ( 90.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 10.00 % " "Info: Total interconnect delay = 0.100 ns ( 10.00 % )" {  } {  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.000 ns" { framecontrol:inst4|div3[1] framecontrol:inst4|div3co } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "12.600 ns" { clk barker:inst7|temp[6] decoder:inst2|reduce_nor~117 decoder:inst2|reduce_nor~118 decoder:inst2|reduce_nor~119 framecontrol:inst4|s~121 framecontrol:inst4|clk3 framecontrol:inst4|div3co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "6.100 ns" { clk cnt32:inst|co framecontrol:inst4|clk3 framecontrol:inst4|div3[1] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.000 ns" { framecontrol:inst4|div3[1] framecontrol:inst4|div3co } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "framecontrol:inst4\|div3\[0\] clk clk 4.000 ns register " "Info: tsu for register framecontrol:inst4\|div3\[0\] (data pin = clk, clock pin = clk) is 4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest pin register " "Info: + Longest pin to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framesynch.bdf" "" "" { Schematic "D:/lzxdesign10/framesynch/framesynch.bdf" { { 48 -96 72 64 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(5.600 ns) 6.900 ns framecontrol:inst4\|s~121 2 COMB LOOP LC1_A3 13 " "Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 6.900 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4\|s~121'" { { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|s~121 LC1_A3 " "Info: Loc. = LC1_A3; Node framecontrol:inst4\|s~121" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|s~121 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|temq~379 LC2_A3 " "Info: Loc. = LC2_A3; Node framecontrol:inst4\|temq~379" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temq~379 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_PART_OF_SCC" "framecontrol:inst4\|temnq~330 LC7_A3 " "Info: Loc. = LC7_A3; Node framecontrol:inst4\|temnq~330" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temnq~330 } "NODE_NAME" } } }  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|s~121 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temq~379 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { framecontrol:inst4|temnq~330 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "5.600 ns" { clk framecontrol:inst4|s~121 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 8.400 ns framecontrol:inst4\|div3\[1\]~17 3 COMB LC8_A3 2 " "Info: 3: + IC(0.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC8_A3; Fanout = 2; COMB Node = 'framecontrol:inst4\|div3\[1\]~17'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "1.500 ns" { framecontrol:inst4|s~121 framecontrol:inst4|div3[1]~17 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.500 ns) 9.000 ns framecontrol:inst4\|div3\[0\] 4 REG LC5_A3 3 " "Info: 4: + IC(0.100 ns) + CELL(0.500 ns) = 9.000 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4\|div3\[0\]'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "0.600 ns" { framecontrol:inst4|div3[1]~17 framecontrol:inst4|div3[0] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns 97.78 % " "Info: Total cell delay = 8.800 ns ( 97.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 2.22 % " "Info: Total interconnect delay = 0.200 ns ( 2.22 % )" {  } {  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "9.000 ns" { clk framecontrol:inst4|s~121 framecontrol:inst4|div3[1]~17 framecontrol:inst4|div3[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.100 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 6.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 19 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framesynch.bdf" "" "" { Schematic "D:/lzxdesign10/framesynch/framesynch.bdf" { { 48 -96 72 64 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.500 ns) 3.900 ns cnt32:inst\|co 2 REG LC2_A5 5 " "Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst\|co'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.600 ns" { clk cnt32:inst|co } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/cnt32.vhd" "" "" { Text "D:/lzxdesign10/framesynch/cnt32.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.400 ns) 6.000 ns framecontrol:inst4\|clk3 3 COMB LC6_A3 3 " "Info: 3: + IC(0.700 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4\|clk3'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "2.100 ns" { cnt32:inst|co framecontrol:inst4|clk3 } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.000 ns) 6.100 ns framecontrol:inst4\|div3\[0\] 4 REG LC5_A3 3 " "Info: 4: + IC(0.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4\|div3\[0\]'" {  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "0.100 ns" { framecontrol:inst4|clk3 framecontrol:inst4|div3[0] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns 52.46 % " "Info: Total cell delay = 3.200 ns ( 52.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 47.54 % " "Info: Total interconnect delay = 2.900 ns ( 47.54 % )" {  } {  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "6.100 ns" { clk cnt32:inst|co framecontrol:inst4|clk3 framecontrol:inst4|div3[0] } "NODE_NAME" } } }  } 0}  } { { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "9.000 ns" { clk framecontrol:inst4|s~121 framecontrol:inst4|div3[1]~17 framecontrol:inst4|div3[0] } "NODE_NAME" } } } { "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" "" "" { Report "D:/lzxdesign10/framesynch/db/framesynch_cmp.qrpt" Compiler "framesynch" "UNKNOWN" "V1" "D:/lzxdesign10/framesynch/db/framesynch.quartus_db" { Floorplan "" "" "6.100 ns" { clk cnt32:inst|co framecontrol:inst4|clk3 framecontrol:inst4|div3[0] } "NODE_NAME" } } }  } 0}
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