framesynch.tan.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITAN_SCC_LOOP" "3 " "Info: Found combinational loop of 3 nodes" { { "Info" "ITAN_SCC_NODE" "framecontrol:inst4\|s~121 " "Info: Node framecontrol:inst4\|s~121" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "framecontrol:inst4\|temq~379 " "Info: Node framecontrol:inst4\|temq~379" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } }  } 0} { "Info" "ITAN_SCC_NODE" "framecontrol:inst4\|temnq~330 " "Info: Node framecontrol:inst4\|temnq~330" {  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } }  } 0}  } { { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 15 -1 0 } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } } { "D:/lzxdesign10/framesynch/framecontrol.vhd" "" "" { Text "D:/lzxdesign10/framesynch/framecontrol.vhd" 26 -1 0 } }  } 0}