cnt32.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 31 行

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt32 is
  port(clk,en:in std_logic;
       co:out std_logic);
end cnt32;

architecture behvcnt of cnt32 is
  signal countx:std_logic_vector(4 downto 0);
begin 
  process(clk,en)
  begin
    if  (en='1')  then
       countx<="00000";
       co<='0';
    elsif (clk'event and clk='1')  then
      if (en='0') then
          if (countx="11111") then
             countx<="00000";
             co<='1';
          else
             countx<=countx+'1';
             co<='0';
          end if;
       end if;
      end if;
  end process;
end behvcnt;