framesynch.map.summary

来自「《CPLD_FPGA设计及应用》课件与实例」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Wed Apr 05 21:52:51 2006
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : framesynch
Top-level Entity Name : framesynch
Family : FLEX10KA
Device : EPF10K10AFC256-1
Timing Models : Production
Total logic elements : 27
Total pins : 3
Total memory bits : 0