framecontrol.vhd

《CPLD_FPGA设计及应用》课件与实例

library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity framecontrol is 
  port(div32,idtin:in std_logic;
       ck:in std_logic;
       q:out std_logic;
       div32en:out std_logic;
       glt:out std_logic_vector(2 downto 0));
end framecontrol;

architecture fctrl of framecontrol is 
  --signal ck,r,s:std_logic;
  signal r,s:std_logic;
  signal temq,temnq:std_logic;
  signal clk3,en3,div3co:std_logic;
  signal div3:std_logic_vector(1 downto 0);
begin
 -- p1:process(clk)
 --    begin 
 --      if (clk'event and clk='1') then
 --          ck<='1';
 --      end if;
 --    end process;
  p2:process(ck,r,s,temq,temnq)
     begin
       if ck='0' then 
          temq<='1';
          temnq<='0';
       elsif (s='1' and r='0') then
          temq<='1';
          temnq<='0';
       elsif (s='0' and r='1') then
          temq<='0';
          temnq<='1'; 
       elsif (s='0' and r='0') then
          temq<=temq;
          temnq<=temnq;
       end if;
    q<=temq;
  end process;
  s<=idtin and (div32 or temnq);
  r<=div3co;
  en3<=s;
  clk3<=div32 and (not s); 
  div32en<=idtin and s;
p3:process(en3,clk3)
   begin
     if (en3='1') then
       div3co<='1';
     elsif(clk3'event and clk3='1')  then
       if (div3="11") then
         div3co<='1'; 
         div3<="00";
       else
         div3<=div3+'1';
         div3co<='0'; 
       end if; 
     end if;
   end process;
p4:process(temq)
   begin
     if(temq='0') then
       glt<="111";
     else
       glt<="110";
     end if;
   end process;  

end fctrl;