framesynch.map.rpt

《CPLD_FPGA设计及应用》课件与实例

;    |framecontrol:inst4|                   ; 8 (8)       ; 3            ; 0           ; 0    ; 5 (5)        ; 1 (1)             ; 2 (2)            ; 0 (0)           ; |framesynch|framecontrol:inst4                                                 ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+--------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/lzxdesign10/framesynch/framesynch.map.eqn.


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                              ;
+-------------------------------------------------------------------+-----------------+
; File Name                                                         ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; barker.vhd                                                        ; yes             ;
; decoder.vhd                                                       ; yes             ;
; framecontrol.vhd                                                  ; yes             ;
; framesynch.bdf                                                    ; yes             ;
; cnt32.vhd                                                         ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc      ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/flex10ke_lcell.inc    ; yes             ;
+-------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 27      ;
; Total combinational functions     ; 19      ;
; Total 4-input functions           ; 7       ;
; Total 3-input functions           ; 1       ;
; Total 2-input functions           ; 5       ;
; Total 1-input functions           ; 1       ;
; Total 0-input functions           ; 5       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 16      ;
; Total logic cells in carry chains ; 5       ;
; I/O pins                          ; 3       ;
; Maximum fan-out node              ; clk     ;
; Maximum fan-out                   ; 15      ;
; Total fan-out                     ; 81      ;
; Average fan-out                   ; 2.70    ;
+-----------------------------------+---------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 7     ;
; Number of synthesis-generated cells                    ; 20    ;
; Number of WYSIWYG LUTs                                 ; 7     ;
; Number of synthesis-generated LUTs                     ; 12    ;
; Number of WYSIWYG registers                            ; 5     ;
; Number of synthesis-generated registers                ; 11    ;
; Number of cells with combinational logic only          ; 11    ;
; Number of cells with registers only                    ; 8     ;
; Number of cells with combinational logic and registers ; 8     ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 7     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 2     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Apr 05 21:52:45 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off framesynch -c framesynch
Info: Found 2 design units, including 1 entities, in source file barker.vhd
    Info: Found design unit 1: barker-recogbk
    Info: Found entity 1: barker
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
    Info: Found design unit 1: decoder-decoderbk
    Info: Found entity 1: decoder
Info: Found 2 design units, including 1 entities, in source file framecontrol.vhd
    Info: Found design unit 1: framecontrol-fctrl
    Info: Found entity 1: framecontrol
Info: Found 1 design units, including 1 entities, in source file framesynch.bdf
    Info: Found entity 1: framesynch
Info: Found 2 design units, including 1 entities, in source file cnt32.vhd
    Info: Found design unit 1: cnt32-behvcnt
    Info: Found entity 1: cnt32
Warning: VHDL Process Statement warning at framecontrol.vhd(26): signal or variable temq may not be assigned a new value in every possible path through the Process Statement. Signal or variable temq holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at framecontrol.vhd(26): signal or variable temnq may not be assigned a new value in every possible path through the Process Statement. Signal or variable temnq holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: cnt32:inst|countx[0]~5
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Ignored 2 buffer(s)
    Info: Ignored 2 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Info: Implemented 30 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 27 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Apr 05 21:52:51 2006
    Info: Elapsed time: 00:00:06