framesynch.tan.summary

《CPLD_FPGA设计及应用》课件与实例

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : clk
To             : framecontrol:inst4|div3[1]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 23.600 ns
From           : framecontrol:inst4|div3co
To             : fsynout
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 14.400 ns
From           : clk
To             : fsynout
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.200 ns
From           : clk
To             : framecontrol:inst4|div3[1]
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.100 ns
From           : cnt32:inst|co
To             : fsynout
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 14.400 ns
From           : clk
To             : fsynout
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 75.76 MHz ( period = 13.200 ns )
From           : framecontrol:inst4|div3co
To             : framecontrol:inst4|div3[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : framecontrol:inst4|div3[0]
To             : framecontrol:inst4|div3[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 23

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 23

--------------------------------------------------------------------------------------