framesynch.vhd

《CPLD_FPGA设计及应用》课件与实例

-- Copyright (C) 1991-2004 Altera Corporation
-- Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
-- support information,  device programming or simulation file,  and any other
-- associated  documentation or information  provided by  Altera  or a partner
-- under  Altera's   Megafunction   Partnership   Program  may  be  used  only
-- to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
-- other  use  of such  megafunction  design,  netlist,  support  information,
-- device programming or simulation file,  or any other  related documentation
-- or information  is prohibited  for  any  other purpose,  including, but not
-- limited to  modification,  reverse engineering,  de-compiling, or use  with
-- any other  silicon devices,  unless such use is  explicitly  licensed under
-- a separate agreement with  Altera  or a megafunction partner.  Title to the
-- intellectual property,  including patents,  copyrights,  trademarks,  trade
-- secrets,  or maskworks,  embodied in any such megafunction design, netlist,
-- support  information,  device programming or simulation file,  or any other
-- related documentation or information provided by  Altera  or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.

-- PROGRAM "Quartus II"
-- VERSION "Version 4.1 Build 181 06/29/2004 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY framesynch IS 
	port
	(
		clk :  IN  STD_LOGIC;
		codein :  IN  STD_LOGIC;
		fsynout :  OUT  STD_LOGIC
	);
END framesynch;

ARCHITECTURE bdf_type OF framesynch IS 

component cnt32
	PORT(clk : IN STD_LOGIC;
		 en : IN STD_LOGIC;
		 co : OUT STD_LOGIC
	);
end component;

component decoder
	PORT(glt : IN STD_LOGIC_VECTOR(2 downto 0);
		 rbk : IN STD_LOGIC_VECTOR(6 downto 0);
		 rcgout : OUT STD_LOGIC
	);
end component;

component framecontrol
	PORT(div32 : IN STD_LOGIC;
		 idtin : IN STD_LOGIC;
		 ck : IN STD_LOGIC;
		 q : OUT STD_LOGIC;
		 div32en : OUT STD_LOGIC;
		 glt : OUT STD_LOGIC_VECTOR(2 downto 0)
	);
end component;

component barker
	PORT(clk : IN STD_LOGIC;
		 codein : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(6 downto 0)
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(2 downto 0);
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(6 downto 0);
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;


BEGIN 



b2v_inst : cnt32
PORT MAP(clk => clk,
		 en => SYNTHESIZED_WIRE_0,
		 co => SYNTHESIZED_WIRE_7);

b2v_inst2 : decoder
PORT MAP(glt => SYNTHESIZED_WIRE_1,
		 rbk => SYNTHESIZED_WIRE_2,
		 rcgout => SYNTHESIZED_WIRE_4);

b2v_inst4 : framecontrol
PORT MAP(div32 => SYNTHESIZED_WIRE_7,
		 idtin => SYNTHESIZED_WIRE_4,
		 ck => clk,
		 q => SYNTHESIZED_WIRE_5,
		 div32en => SYNTHESIZED_WIRE_0,
		 glt => SYNTHESIZED_WIRE_1);

fsynout <= SYNTHESIZED_WIRE_5 AND SYNTHESIZED_WIRE_7;

b2v_inst7 : barker
PORT MAP(clk => clk,
		 codein => codein,
		 q => SYNTHESIZED_WIRE_2);

END;