framesynch.tan.rpt

《CPLD_FPGA设计及应用》课件与实例

        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4|div3[1]'
        Info: 2: + IC(0.100 ns) + CELL(0.900 ns) = 1.000 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
        Info: Total cell delay = 0.900 ns ( 90.00 % )
        Info: Total interconnect delay = 0.100 ns ( 10.00 % )
    Info: + Micro hold delay of destination is 0.600 ns
Info: tsu for register framecontrol:inst4|div3[0] (data pin = clk, clock pin = clk) is 4.000 ns
    Info: + Longest pin to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 6.900 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 3: + IC(0.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC8_A3; Fanout = 2; COMB Node = 'framecontrol:inst4|div3[1]~17'
        Info: 4: + IC(0.100 ns) + CELL(0.500 ns) = 9.000 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4|div3[0]'
        Info: Total cell delay = 8.800 ns ( 97.78 % )
        Info: Total interconnect delay = 0.200 ns ( 2.22 % )
    Info: + Micro setup delay of destination is 1.100 ns
    Info: - Shortest clock path from clock clk to destination register is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst|co'
        Info: 3: + IC(0.700 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
        Info: 4: + IC(0.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4|div3[0]'
        Info: Total cell delay = 3.200 ns ( 52.46 % )
        Info: Total interconnect delay = 2.900 ns ( 47.54 % )
Info: tco from clock clk to destination pin fsynout through register framecontrol:inst4|div3co is 23.600 ns
    Info: + Longest clock path from clock clk to source register is 12.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 3; REG Node = 'barker:inst7|temp[6]'
        Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC4_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~117'
        Info: 4: + IC(0.100 ns) + CELL(1.300 ns) = 7.600 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~118'
        Info: 5: + IC(0.100 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC8_A1; Fanout = 3; COMB Node = 'decoder:inst2|reduce_nor~119'
        Info: 6: + IC(0.000 ns) + CELL(2.400 ns) = 11.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 7: + IC(0.100 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
        Info: 8: + IC(0.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
        Info: Total cell delay = 9.200 ns ( 73.02 % )
        Info: Total interconnect delay = 3.400 ns ( 26.98 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 10.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
        Info: 2: + IC(0.000 ns) + CELL(4.500 ns) = 4.500 ns; Loc. = LC2_A3; Fanout = 3; COMB LOOP Node = 'framecontrol:inst4|temq~379'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.800 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'inst6'
        Info: 4: + IC(0.600 ns) + CELL(3.100 ns) = 10.500 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'fsynout'
        Info: Total cell delay = 9.000 ns ( 85.71 % )
        Info: Total interconnect delay = 1.500 ns ( 14.29 % )
Info: Longest tpd from source pin clk to destination pin fsynout is 14.400 ns
    Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
    Info: 2: + IC(0.000 ns) + CELL(7.100 ns) = 8.400 ns; Loc. = LC2_A3; Fanout = 3; COMB LOOP Node = 'framecontrol:inst4|temq~379'
        Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
        Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
        Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
    Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 10.700 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'inst6'
    Info: 4: + IC(0.600 ns) + CELL(3.100 ns) = 14.400 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'fsynout'
    Info: Total cell delay = 12.900 ns ( 89.58 % )
    Info: Total interconnect delay = 1.500 ns ( 10.42 % )
Info: th for register framecontrol:inst4|div3[0] (data pin = clk, clock pin = clk) is 4.200 ns
    Info: + Longest clock path from clock clk to destination register is 12.600 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 3; REG Node = 'barker:inst7|temp[6]'
        Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC4_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~117'
        Info: 4: + IC(0.100 ns) + CELL(1.300 ns) = 7.600 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~118'
        Info: 5: + IC(0.100 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC8_A1; Fanout = 3; COMB Node = 'decoder:inst2|reduce_nor~119'
        Info: 6: + IC(0.000 ns) + CELL(2.400 ns) = 11.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 7: + IC(0.100 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
        Info: 8: + IC(0.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4|div3[0]'
        Info: Total cell delay = 9.200 ns ( 73.02 % )
        Info: Total interconnect delay = 3.400 ns ( 26.98 % )
    Info: + Micro hold delay of destination is 0.600 ns
    Info: - Shortest pin to register delay is 9.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(5.600 ns) = 6.900 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 3: + IC(0.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC8_A3; Fanout = 2; COMB Node = 'framecontrol:inst4|div3[1]~17'
        Info: 4: + IC(0.100 ns) + CELL(0.500 ns) = 9.000 ns; Loc. = LC5_A3; Fanout = 3; REG Node = 'framecontrol:inst4|div3[0]'
        Info: Total cell delay = 8.800 ns ( 97.78 % )
        Info: Total interconnect delay = 0.200 ns ( 2.22 % )
Info: Minimum tco from clock clk to destination pin fsynout through register cnt32:inst|co is 9.100 ns
    Info: + Shortest clock path from clock clk to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
        Info: 2: + IC(2.100 ns) + CELL(0.000 ns) = 3.400 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst|co'
        Info: Total cell delay = 1.300 ns ( 38.24 % )
        Info: Total interconnect delay = 2.100 ns ( 61.76 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Shortest register to pin delay is 5.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst|co'
        Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 1.500 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'inst6'
        Info: 3: + IC(0.600 ns) + CELL(3.100 ns) = 5.200 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'fsynout'
        Info: Total cell delay = 4.500 ns ( 86.54 % )
        Info: Total interconnect delay = 0.700 ns ( 13.46 % )
Info: Shortest tpd from source pin clk to destination pin fsynout is 14.400 ns
    Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
    Info: 2: + IC(0.000 ns) + CELL(7.100 ns) = 8.400 ns; Loc. = LC2_A3; Fanout = 3; COMB LOOP Node = 'framecontrol:inst4|temq~379'
        Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
        Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
        Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
    Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 10.700 ns; Loc. = LC1_A5; Fanout = 1; COMB Node = 'inst6'
    Info: 4: + IC(0.600 ns) + CELL(3.100 ns) = 14.400 ns; Loc. = PIN_D3; Fanout = 0; PIN Node = 'fsynout'
    Info: Total cell delay = 12.900 ns ( 89.58 % )
    Info: Total interconnect delay = 1.500 ns ( 10.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Wed Apr 05 21:53:03 2006
    Info: Elapsed time: 00:00:01