framesynch.tan.rpt

《CPLD_FPGA设计及应用》课件与实例

; Minimum tco                                                                                          ;
+---------------+------------------+----------------+---------------------------+---------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From                      ; To      ; From Clock ;
+---------------+------------------+----------------+---------------------------+---------+------------+
; N/A           ; None             ; 9.100 ns       ; cnt32:inst|co             ; fsynout ; clk        ;
; N/A           ; None             ; 13.500 ns      ; barker:inst7|temp[1]      ; fsynout ; clk        ;
; N/A           ; None             ; 15.400 ns      ; barker:inst7|temp[0]      ; fsynout ; clk        ;
; N/A           ; None             ; 15.500 ns      ; barker:inst7|temp[6]      ; fsynout ; clk        ;
; N/A           ; None             ; 16.200 ns      ; barker:inst7|temp[4]      ; fsynout ; clk        ;
; N/A           ; None             ; 16.300 ns      ; barker:inst7|temp[3]      ; fsynout ; clk        ;
; N/A           ; None             ; 16.300 ns      ; barker:inst7|temp[2]      ; fsynout ; clk        ;
; N/A           ; None             ; 16.300 ns      ; barker:inst7|temp[5]      ; fsynout ; clk        ;
; N/A           ; None             ; 17.100 ns      ; framecontrol:inst4|div3co ; fsynout ; clk        ;
+---------------+------------------+----------------+---------------------------+---------+------------+


+----------------------------------------------------------------------+
; Minimum tpd                                                          ;
+---------------+-------------------+-----------------+------+---------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To      ;
+---------------+-------------------+-----------------+------+---------+
; N/A           ; None              ; 14.400 ns       ; clk  ; fsynout ;
+---------------+-------------------+-----------------+------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Apr 05 21:53:02 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off framesynch -c framesynch
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 3 nodes
    Info: Node framecontrol:inst4|s~121
    Info: Node framecontrol:inst4|temq~379
    Info: Node framecontrol:inst4|temnq~330
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Warning: Found 15 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock decoder:inst2|reduce_nor~24 as buffer
    Info: Detected gated clock decoder:inst2|reduce_nor~118 as buffer
    Info: Detected ripple clock barker:inst7|temp[3] as buffer
    Info: Detected gated clock decoder:inst2|reduce_nor~117 as buffer
    Info: Detected ripple clock barker:inst7|temp[2] as buffer
    Info: Detected ripple clock barker:inst7|temp[0] as buffer
    Info: Detected ripple clock barker:inst7|temp[4] as buffer
    Info: Detected ripple clock barker:inst7|temp[6] as buffer
    Info: Detected ripple clock barker:inst7|temp[5] as buffer
    Info: Detected gated clock framecontrol:inst4|clk3 as buffer
    Info: Detected gated clock decoder:inst2|reduce_nor~119 as buffer
    Info: Detected ripple clock barker:inst7|temp[1] as buffer
    Info: Detected ripple clock framecontrol:inst4|div3co as buffer
    Info: Detected gated clock framecontrol:inst4|s~121 as buffer
    Info: Detected ripple clock cnt32:inst|co as buffer
Info: Clock clk has Internal fmax of 75.76 MHz between source register framecontrol:inst4|div3co and destination register framecontrol:inst4|div3[1] (period= 13.2 ns)
    Info: + Longest register to register delay is 5.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
        Info: 2: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
            Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
            Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
            Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
        Info: 3: + IC(0.100 ns) + CELL(1.400 ns) = 4.500 ns; Loc. = LC8_A3; Fanout = 2; COMB Node = 'framecontrol:inst4|div3[1]~17'
        Info: 4: + IC(0.100 ns) + CELL(0.500 ns) = 5.100 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4|div3[1]'
        Info: Total cell delay = 4.900 ns ( 96.08 % )
        Info: Total interconnect delay = 0.200 ns ( 3.92 % )
    Info: - Smallest clock skew is -6.500 ns
        Info: + Shortest clock path from clock clk to destination register is 6.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst|co'
            Info: 3: + IC(0.700 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
            Info: 4: + IC(0.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4|div3[1]'
            Info: Total cell delay = 3.200 ns ( 52.46 % )
            Info: Total interconnect delay = 2.900 ns ( 47.54 % )
        Info: - Longest clock path from clock clk to source register is 12.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 3; REG Node = 'barker:inst7|temp[6]'
            Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC4_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~117'
            Info: 4: + IC(0.100 ns) + CELL(1.300 ns) = 7.600 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~118'
            Info: 5: + IC(0.100 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC8_A1; Fanout = 3; COMB Node = 'decoder:inst2|reduce_nor~119'
            Info: 6: + IC(0.000 ns) + CELL(2.400 ns) = 11.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
                Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
                Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
                Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
            Info: 7: + IC(0.100 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
            Info: 8: + IC(0.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
            Info: Total cell delay = 9.200 ns ( 73.02 % )
            Info: Total interconnect delay = 3.400 ns ( 26.98 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 1.100 ns
Warning: Circuit may not operate. Detected 23 non-operational path(s) clocked by clock clk with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register framecontrol:inst4|div3[1] and destination pin or register framecontrol:inst4|div3co for clock clk (Hold time is 5.6 ns)
    Info: + Largest clock skew is 6.500 ns
        Info: + Longest clock path from clock clk to destination register is 12.600 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC1_A11; Fanout = 3; REG Node = 'barker:inst7|temp[6]'
            Info: 3: + IC(0.900 ns) + CELL(1.400 ns) = 6.200 ns; Loc. = LC4_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~117'
            Info: 4: + IC(0.100 ns) + CELL(1.300 ns) = 7.600 ns; Loc. = LC6_A1; Fanout = 1; COMB Node = 'decoder:inst2|reduce_nor~118'
            Info: 5: + IC(0.100 ns) + CELL(0.900 ns) = 8.600 ns; Loc. = LC8_A1; Fanout = 3; COMB Node = 'decoder:inst2|reduce_nor~119'
            Info: 6: + IC(0.000 ns) + CELL(2.400 ns) = 11.000 ns; Loc. = LC1_A3; Fanout = 13; COMB LOOP Node = 'framecontrol:inst4|s~121'
                Info: Loc. = LC1_A3; Node framecontrol:inst4|s~121
                Info: Loc. = LC2_A3; Node framecontrol:inst4|temq~379
                Info: Loc. = LC7_A3; Node framecontrol:inst4|temnq~330
            Info: 7: + IC(0.100 ns) + CELL(1.400 ns) = 12.500 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
            Info: 8: + IC(0.100 ns) + CELL(0.000 ns) = 12.600 ns; Loc. = LC3_A3; Fanout = 4; REG Node = 'framecontrol:inst4|div3co'
            Info: Total cell delay = 9.200 ns ( 73.02 % )
            Info: Total interconnect delay = 3.400 ns ( 26.98 % )
        Info: - Shortest clock path from clock clk to source register is 6.100 ns
            Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 19; CLK Node = 'clk'
            Info: 2: + IC(2.100 ns) + CELL(0.500 ns) = 3.900 ns; Loc. = LC2_A5; Fanout = 5; REG Node = 'cnt32:inst|co'
            Info: 3: + IC(0.700 ns) + CELL(1.400 ns) = 6.000 ns; Loc. = LC6_A3; Fanout = 3; COMB Node = 'framecontrol:inst4|clk3'
            Info: 4: + IC(0.100 ns) + CELL(0.000 ns) = 6.100 ns; Loc. = LC4_A3; Fanout = 2; REG Node = 'framecontrol:inst4|div3[1]'
            Info: Total cell delay = 3.200 ns ( 52.46 % )
            Info: Total interconnect delay = 2.900 ns ( 47.54 % )
    Info: - Micro clock to output delay of source is 0.500 ns
    Info: - Shortest register to register delay is 1.000 ns