bitstd.fit.summary

来自「《CPLD_FPGA设计及应用》课件与实例」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Tue Apr 04 20:50:57 2006
Quartus II Version : 4.1 Build 181 06/29/2004 SJ Full Version
Revision Name : bitstd
Top-level Entity Name : bitstd
Family : FLEX10KA
Device : EPF10K10AFC256-1
Timing Models : Production
Total logic elements : 2 / 576 ( < 1 % )
Total pins : 3 / 150 ( 2 % )
Total memory bits : 0 / 6,144 ( 0 % )