bitstd.map.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 04 20:50:53 2006 " "Info: Processing started: Tue Apr 04 20:50:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off bitstd -c bitstd " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off bitstd -c bitstd" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "bitstd.bdf 1 1 " "Info: Using design file bitstd.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 bitstd " "Info: Found entity 1: bitstd" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "bitstd" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "5 " "Info: Implemented 5 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "2 " "Info: Implemented 2 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 04 20:50:54 2006 " "Info: Processing ended: Tue Apr 04 20:50:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}