bitstd.tan.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "ITDB_FULL_TCO_RESULT" "clk out inst 9.200 ns register " "Info: tco from clock clk to destination pin out through register inst is 9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 112 80 248 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 3.400 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.100 ns) + CELL(0.000 ns) = 3.400 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "2.100 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 38.24 % " "Info: Total cell delay = 1.300 ns ( 38.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 61.76 % " "Info: Total interconnect delay = 2.100 ns ( 61.76 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns + Longest register pin " "Info: + Longest register to pin delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst 1 REG LC1_A9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 1.500 ns inst1 2 COMB LC3_A9 1 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 1.500 ns; Loc. = LC3_A9; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "1.500 ns" { inst inst1 } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 72 392 456 120 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.100 ns) 5.300 ns out 3 PIN PIN_E2 0 " "Info: 3: + IC(0.700 ns) + CELL(3.100 ns) = 5.300 ns; Loc. = PIN_E2; Fanout = 0; PIN Node = 'out'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { inst1 out } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 88 488 664 104 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 84.91 % " "Info: Total cell delay = 4.500 ns ( 84.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 15.09 % " "Info: Total interconnect delay = 0.800 ns ( 15.09 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.300 ns" { inst inst1 out } "NODE_NAME" } } }  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.300 ns" { inst inst1 out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "din out 9.400 ns Longest " "Info: Longest tpd from source pin din to destination pin out is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_B9 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 2; PIN Node = 'din'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 96 80 248 112 "din" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.400 ns) 5.600 ns inst1 2 COMB LC3_A9 1 " "Info: 2: + IC(2.900 ns) + CELL(1.400 ns) = 5.600 ns; Loc. = LC3_A9; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "4.300 ns" { din inst1 } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 72 392 456 120 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.100 ns) 9.400 ns out 3 PIN PIN_E2 0 " "Info: 3: + IC(0.700 ns) + CELL(3.100 ns) = 9.400 ns; Loc. = PIN_E2; Fanout = 0; PIN Node = 'out'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { inst1 out } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 88 488 664 104 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 61.70 % " "Info: Total cell delay = 5.800 ns ( 61.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns 38.30 % " "Info: Total interconnect delay = 3.600 ns ( 38.30 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "9.400 ns" { din inst1 out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "inst din clk -1.100 ns register " "Info: th for register inst (data pin = din, clock pin = clk) is -1.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 112 80 248 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 3.400 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.100 ns) + CELL(0.000 ns) = 3.400 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "2.100 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 38.24 % " "Info: Total cell delay = 1.300 ns ( 38.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 61.76 % " "Info: Total interconnect delay = 2.100 ns ( 61.76 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.600 ns + " "Info: + Micro hold delay of destination is 0.600 ns" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_B9 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 2; PIN Node = 'din'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 96 80 248 112 "din" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.100 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.100 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { din inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 43.14 % " "Info: Total cell delay = 2.200 ns ( 43.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 56.86 % " "Info: Total interconnect delay = 2.900 ns ( 56.86 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.100 ns" { din inst } "NODE_NAME" } } }  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.100 ns" { din inst } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk out inst 9.200 ns register " "Info: Minimum tco from clock clk to destination pin out through register inst is 9.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 112 80 248 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 3.400 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.100 ns) + CELL(0.000 ns) = 3.400 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "2.100 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 38.24 % " "Info: Total cell delay = 1.300 ns ( 38.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 61.76 % " "Info: Total interconnect delay = 2.100 ns ( 61.76 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.300 ns + Shortest register pin " "Info: + Shortest register to pin delay is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns inst 1 REG LC1_A9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(1.400 ns) 1.500 ns inst1 2 COMB LC3_A9 1 " "Info: 2: + IC(0.100 ns) + CELL(1.400 ns) = 1.500 ns; Loc. = LC3_A9; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "1.500 ns" { inst inst1 } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 72 392 456 120 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.100 ns) 5.300 ns out 3 PIN PIN_E2 0 " "Info: 3: + IC(0.700 ns) + CELL(3.100 ns) = 5.300 ns; Loc. = PIN_E2; Fanout = 0; PIN Node = 'out'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { inst1 out } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 88 488 664 104 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.500 ns 84.91 % " "Info: Total cell delay = 4.500 ns ( 84.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.800 ns 15.09 % " "Info: Total interconnect delay = 0.800 ns ( 15.09 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.300 ns" { inst inst1 out } "NODE_NAME" } } }  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.300 ns" { inst inst1 out } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "din out 9.400 ns Shortest " "Info: Shortest tpd from source pin din to destination pin out is 9.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_B9 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 2; PIN Node = 'din'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 96 80 248 112 "din" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.400 ns) 5.600 ns inst1 2 COMB LC3_A9 1 " "Info: 2: + IC(2.900 ns) + CELL(1.400 ns) = 5.600 ns; Loc. = LC3_A9; Fanout = 1; COMB Node = 'inst1'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "4.300 ns" { din inst1 } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 72 392 456 120 "inst1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.100 ns) 9.400 ns out 3 PIN PIN_E2 0 " "Info: 3: + IC(0.700 ns) + CELL(3.100 ns) = 9.400 ns; Loc. = PIN_E2; Fanout = 0; PIN Node = 'out'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { inst1 out } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 88 488 664 104 "out" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.800 ns 61.70 % " "Info: Total cell delay = 5.800 ns ( 61.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns 38.30 % " "Info: Total interconnect delay = 3.600 ns ( 38.30 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "9.400 ns" { din inst1 out } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 04 20:51:02 2006 " "Info: Processing ended: Tue Apr 04 20:51:02 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}