bitstd.tan.qmsg

《CPLD_FPGA设计及应用》课件与实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 04 20:51:01 2006 " "Info: Processing started: Tue Apr 04 20:51:01 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off bitstd -c bitstd " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off bitstd -c bitstd" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 112 80 248 128 "clk" "" } } } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register paths exist for clock clk" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "inst din clk 2.800 ns register " "Info: tsu for register inst (data pin = din, clock pin = clk) is 2.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns + Longest pin register " "Info: + Longest pin to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_B9 2 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_B9; Fanout = 2; PIN Node = 'din'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 96 80 248 112 "din" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.900 ns) 5.100 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.900 ns) + CELL(0.900 ns) = 5.100 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.800 ns" { din inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 43.14 % " "Info: Total cell delay = 2.200 ns ( 43.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns 56.86 % " "Info: Total interconnect delay = 2.900 ns ( 56.86 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.100 ns" { din inst } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_L8; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 112 80 248 128 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 3.400 ns inst 2 REG LC1_A9 1 " "Info: 2: + IC(2.100 ns) + CELL(0.000 ns) = 3.400 ns; Loc. = LC1_A9; Fanout = 1; REG Node = 'inst'" {  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "2.100 ns" { clk inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/bitstd.bdf" "" "" { Schematic "d:/lzxdesign8/bitstd/bitstd.bdf" { { 80 288 352 160 "inst" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 38.24 % " "Info: Total cell delay = 1.300 ns ( 38.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns 61.76 % " "Info: Total interconnect delay = 2.100 ns ( 61.76 % )" {  } {  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } }  } 0}  } { { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "5.100 ns" { din inst } "NODE_NAME" } } } { "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" "" "" { Report "d:/lzxdesign8/bitstd/db/bitstd_cmp.qrpt" Compiler "bitstd" "UNKNOWN" "V1" "d:/lzxdesign8/bitstd/db/bitstd.quartus_db" { Floorplan "" "" "3.400 ns" { clk inst } "NODE_NAME" } } }  } 0}