clkdiv.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 34 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY clkdiv IS
  PORT(mclk:IN STD_LOGIC;
       freq:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
       clkout:OUT STD_LOGIC);
END clkdiv;
ARCHITECTURE cdiv OF clkdiv IS
  SIGNAL outtemp:STD_LOGIC_VECTOR(16 DOWNTO 0);
BEGIN
  PROCESS(mclk)
    CONSTANT count:STD_LOGIC_VECTOR(15 DOWNTO 0):=(OTHERS=>'1');
    VARIABLE clktemp:STD_LOGIC;
    VARIABLE freqtemp:STD_LOGIC_VECTOR(15 DOWNTO 0);
    VARIABLE freqcount:STD_LOGIC_VECTOR(15 DOWNTO 0);
  BEGIN
     freqtemp:=count-freq;
       IF (mclk'EVENT AND mclk='1') THEN
         IF(freqcount='0' & freqtemp(15 DOWNTO 1)) THEN
             clktemp:=NOT clktemp;
             freqcount:=freqcount+1;
         ELSIF(freqcount=freqtemp) THEN
             clktemp:=NOT clktemp;
             freqcount:=(OTHERS=>'0');
         ELSE
             freqcount:=freqcount+1;
         END IF;
       END IF;
            clkout<=clktemp;
     END PROCESS ;
END cdiv;