mod360.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY mod360 IS
  PORT(address:IN STD_LOGIC_VECTOR(8 DOWNTO 0);
       addressout:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END mod360;
ARCHITECTURE modx OF mod360 IS
BEGIN
     PROCESS(address)
       VARIABLE temp:STD_LOGIC_VECTOR(8 DOWNTO 0);
     BEGIN
           temp:=temp+120;
       IF (temp<360) THEN
          addressout<=temp;
       ELSE
          addressout<=temp-360;
       END IF;
     END PROCESS;
END modx;