sum99.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SUM99 IS
  PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
       CLK:IN STD_LOGIC;
       EN:IN STD_LOGIC;
       RESET:IN STD_LOGIC;
       OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0));
 END ENTITY SUM8;
ARCHITECTURE ART OF SUM8 IS
  SIGNAL TEMP:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
PROCESS(CLK,EN,RESET)IS
BEGIN
        IF RESET='1'THEN 
TEMP<="0000000000";
ELSE
IF CLK'EVENT AND CLK='1' THEN
IF EN='1'THEN
TEMP<=TEMP+K;
END IF;
END IF;
END IF;
OUT1<=TEMP;
END PROCESS;
END ARCHITECTURE;