rom2.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ROM2 IS
  PORT(ADDR:IN STD_LOGIC_VECTOR( 5 DOWNTO 0);
       CLK:IN STD_LOGIC;
       OUTP:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY ROM2;
ARCHITECTURE ART OF ROM2 IS
BEGIN
PROCESS(CLK)IS
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
  CASE ADDR IS
WHEN "000000"=>OUTP<="00000001";
WHEN "000001"=>OUTP<="00000001";
WHEN "000010"=>OUTP<="00000001";
WHEN "000011"=>OUTP<="00000001";
……
WHEN "111011"=>OUTP<="00000100";
WHEN "111100"=>OUTP<="00000100";
WHEN "111101"=>OUTP<="00000100";
WHEN "111110"=>OUTP<="00000100";
WHEN "111111"=>OUTP<="00000100";
WHEN OTHERS=>OUTP<="00000000";
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE ART;