addresscounter.vhd

来自「《CPLD_FPGA设计及应用》课件与实例」· VHDL 代码 · 共 24 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY addresscounter IS
  PORT(clk:IN STD_LOGIC;
       address:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END addresscounter;
ARCHITECTURE addcnt OF addresscounter IS
BEGIN
  PROCESS(clk)
    VARIABLE count:STD_LOGIC_VECTOR(8 DOWNTO 0);
  BEGIN
       IF (clk'EVENT AND clk='1') THEN
         IF(count<359) THEN
             count:=count+1;
         ELSE
             count:=(OTHERS=>'0');
         END IF;
       END IF;
            address<=count;
     END PROCESS ;
END addcnt;